/*
 * Memory Setup stuff - taken from blob memsetup.S
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 *
 * Modified for the Samsung SMDK2410 by
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <config.h>
#include <version.h>
#include "lowlevel_init.h"


_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

.globl lowlevel_init
lowlevel_init:
	/* Set system clock
	 *	FCLK:HCLK:PCLK = 1:4:8 
	 *	FCLK=400MHz，HCLK=100MHz，PCLK=50MHz
	 */
	ldr r0, =CLKDIVN
	mov r1, #5
	str r1, [r0]

/*	set Clocking modes : Asynchronous
 *
 *	if HDIVN is not 0, the CPU bus mode has to be changed 
 *	from the fast bus mode to the asynchronous bus mode 
 *	and S3C2440 does not support synchronous bus mode
 */
	mrc p15, 0, r1, c1, c0, 0
	orr r1, r1, #0xc0000000
	mcr p15, 0, r1, c1, c0, 0
	
/* 
	Setup PLL CONTROL REGISTER 
	NOTE: When you set MPLL & UPLL values
	  you have to set the UPLL value first and then the MPLL value. 
	  (Needs intervalsapproximately 7 NOP )

	Fout = 2 * m * Fin / (p*2^S)
	FVCO = 2 * m * Fin / p		

	where: m=MDIV+8, p=PDIV+2, s=SDIV

	Input Frequency Output-Frequency  MDIV		PDIV	SDIV
	12.0000MHz		405.00 MHz		  127(0x7f)  2		 1
*/
	ldr r1, =MPLLCON
	mov r2, #MDIV_405MHZ
	add r2, r2, #PSDIV_405MHZ
	str r2, [r1]

lowlevel_mem_init:
	/* memory control configuration */
	/* make r0 relative the current location so that it */
	/* reads SMRDATA out of FLASH rather than memory ! */
	/*set up for SDRAM K4S561632N*/
	ldr     r0, =SMRDATA
	ldr		r1, =lowlevel_mem_init
	sub		r0, r0, r1
	adr		r3, lowlevel_mem_init
	add     r0, r0, r3			/*real address of the code*/

	ldr		r1, =BWSCON			/* Bus Width Status Controller */
	add		r2, r0, #13*4
0:
	ldr     r3, [r0], #4
	str     r3, [r1], #4
	cmp     r2, r0
	bne     0b

	/* everything is fine now */
	mov	pc, lr

	.ltorg
/* the literal pools origin */

SMRDATA:
    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
    .word 0xb1	/*memory map 64MB SDRAM*/
    .word 0x30  /*set CAS latency 2 clocks*/
    .word 0x30  /*set CAS latency 2 clocks*/
